| Retiring |
|
|
INST_RETIRED/(IssueBW * CPU_CYCLES) |
INST_RETIRED |
the number of total retired instructions |
| FrontEnd Bound |
|
|
IF_FETCH_BUBBLE/(IssueBW * CPU_CYCLES) |
INST_SPEC |
the number of total instructions that speculatively executed |
|
Fetch Latency Bound |
|
IF_FETCH_BUBBLE_EQ_MAX/CPU_CYCLES |
CPU_CYCLES |
total cycles of all instructions retired |
|
Fetch Bandwidth Bound |
|
FrontEnd bound - Fetch Latency Bound |
IF_FETCH_BUBBLE |
Unutilized issue-pipeline slots while there is no backend-stall |
| Bad Speculation |
|
|
(INST_SPEC - INST_RETIRED + RECOVERY_BUBBLE)/(IssueBW * CPU_CYCLES) |
IF_FETCH_BUBBLE_EQ_MAX |
cycles that fetch 0 instruction from instruction buffer while there is no backend-stall |
|
Branch Missprediction |
|
Bad Speculation * BR_MIS_PRED/TOTAL_FLUSH |
BR_MIS_PRED |
the number of mis-predicted branch instructions |
|
machine clears |
|
Bad Speculation - Branch Mispredicts |
TOTAL FLUSH |
the number of flush event |
| BackEnd bound |
|
|
1 - (FrontEnd Bound + Bad_Speculation + Retiring) |
RECOVERY_BUBBLE |
Unutilized issue-pipeline slots due to recovery from earlier miss-speculation |
|
Core bound |
|
(EXEC_STALL_CYCLE - MEMSTALL_ANYLOAD - MEMSTALL_STORE)/CPU_CYCLE |
EXEC_STALL_CYCLE |
SUM(OpsExecuted[= FEW]) |
|
Memory Bound |
|
(MEMSTALL_ANYLOAD + MEMSTALL_STORE) / CPU_CYCLES |
MEMSTALL_ANY_LOAD |
Cycles with no uops executed and at least X in-flight load that is not completed yet |
|
|
L1 bound |
(MEMSTALL_ANYLOAD - MEMSTALL_L1MISS) / CPU_CYCLES |
MEMSTALL_STORE |
Cycles with few uops executed and no more stores can be issued |
|
|
L2 bound |
(MEMSTALL_L1MISS - MEMSTALL_L2MISS) /CPU_CYCLES |
MEMSTALL_L1MISS |
Cycles with no uops executed and at least 1 in-flight load that has missed the L1-cache |
|
|
L3 bound |
(MEMSTALL_L2MISS - MEMSTALL_L3MISS)/CPU_CYCLES |
MEMSTALL_L2MISS |
Cycles with no uops executed and at least 1 in-flight load that has missed the L2-cache |
|
|
Mem bound |
MEMSTALL_L3MISS/CPU_CYCLES |
MEMSTALL_L3MISS |
Cycles with no uops executed and at least 1 in-flight load that has missed the L2-cache |
|
|
store bound |
MEMSTALL_STORE/CPU_CYCLES |
|
|