GEM5 O3 CPU Fetch Stage Analysis (重构版本)

TimeBuffer<TimeStruct> *timeBuffer;  // Main time buffer for communication

// Wires from other stages to Fetch
TimeBuffer<TimeStruct>::wire fromDecode;   // For stall signals and instruction counts
TimeBuffer<TimeStruct>::wire fromRename;   // For stall signals
TimeBuffer<TimeStruct>::wire fromIEW;      // For stall signals and branch resolution
TimeBuffer<TimeStruct>::wire fromCommit;   // For squash signals and interrupts

// Wire to Decode stage
TimeBuffer<FetchStruct>::wire toDecode;    // For sending fetched instructions

// In tick() method:
// Send instruction packet to decode
if (numInst) {
    toDecode->insts = std::move(insts);
    toDecode->size = numInst;
    wroteToTimeBuffer = true;
}

// In checkSignalsAndUpdate() method:
// Check if the decode stage is stalled
if (fromDecode->decodeStall) {
    stalls[tid].decode = true;
}

// In checkSignalsAndUpdate() method:
// Check for squash from commit
if (fromCommit->commitInfo[tid].squash) {
    DPRINTF(Fetch, "[tid:%i] Squashing from commit.\n", tid);
    squash(fromCommit->commitInfo[tid].pc,
           fromCommit->commitInfo[tid].doneSeqNum,
           fromCommit->commitInfo[tid].squashInst, tid);
}

// Check for commit's interrupt signals
if (fromCommit->commitInfo[tid].interruptPending) {
    interruptPending = true;
}

// In checkSignalsAndUpdate() method:
// Check for squash from IEW (mispredicted branch)
if (fromIEW->iewInfo[tid].squash) {
    DPRINTF(Fetch, "[tid:%i] Squashing from IEW.\n", tid);
    squash(fromIEW->iewInfo[tid].pc,
           fromIEW->iewInfo[tid].doneSeqNum,
           fromIEW->iewInfo[tid].squashInst, tid);
}

bool lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &pc) {
    // Access branch predictor and update PC
    bool predicted_taken = getBp()->predict(inst, pc, inst->pcState());
    // ... additional logic ...
    return predicted_taken;
}

uint8_t *fetchBuffer[MaxThreads];     // Raw instruction data
Addr fetchBufferPC[MaxThreads];       // PC of first instruction in buffer
bool fetchBufferValid[MaxThreads];    // Whether buffer data is valid
unsigned fetchBufferSize;             // Size of fetch buffer in bytes
Addr fetchBufferMask;                 // Mask to align PC to fetch buffer boundary

std::deque<DynInstPtr> fetchQueue[MaxThreads];  // Queue of fetched instructions
unsigned fetchQueueSize;                        // Maximum size of fetch queue

RequestPtr memReq[MaxThreads];        // Primary memory request
RequestPtr anotherMemReq[MaxThreads]; // Used for unaligned access
PacketPtr firstPkt[MaxThreads];       // First packet for I-cache access
PacketPtr secondPkt[MaxThreads];      // Second packet for unaligned access
std::pair<Addr, Addr> accessInfo[MaxThreads];  // Address info for cache access

// Overall fetch status
enum FetchStatus { Active, Inactive } _status;

// Per-thread status
enum ThreadStatus {
    Running, Idle, Squashing, Blocked, Fetching, TrapPending,
    QuiescePending, ItlbWait, IcacheWaitResponse, IcacheWaitRetry,
    IcacheAccessComplete, NoGoodAddr, NumFetchStatus
} fetchStatus[MaxThreads];

// Stall tracking
struct Stalls {
    bool decode;
    bool drain;
} stalls[MaxThreads];

// Stall reason tracking
std::vector<StallReason> stallReason;

branch_prediction::BPredUnit *branchPred;  // Main branch predictor
branch_prediction::stream_pred::DecoupledStreamBPU *dbsp;  // Stream predictor
branch_prediction::ftb_pred::DecoupledBPUWithFTB *dbpftb;  // FTB predictor
branch_prediction::btb_pred::DecoupledBPUWithBTB *dbpbtb;  // BTB predictor

branch_prediction::ftb_pred::LoopBuffer *loopBuffer;  // Loop buffer
bool enableLoopBuffer;                                // Loop buffer enable flag
unsigned currentLoopIter;                             // Current loop iteration counter
bool currentFetchTargetInLoop;                        // If current fetch is in a loop

tick()
  |
  +--> initializeTickState()  // Initialize state for this tick cycle
        |
        +--> checkSignalsAndUpdate()  // Check signals from other stages for all active threads
        |
        +--> Update fetch status distribution stats
        |
        +--> Reset pipelined fetch flags
  |
  +--> fetchAndProcessInstructions()  // Perform fetch operations and instruction delivery
        |
        +--> fetch()  // Fetch instructions from active threads (loop for numFetchingThreads)
        |     |
        |     +--> selectFetchThread()  // Select thread to fetch from
        |     |
        |     +--> checkDecoupledFrontend()  // Check FTQ availability for decoupled frontend
        |     |
        |     +--> prepareFetchAddress()  // Handle status transitions and address preparation
        |     |
        |     +--> performInstructionFetch()  // Main instruction fetching logic
        |           |
        |           +--> Instruction fetch loop (while numInst < fetchWidth)
        |                 |
        |                 +--> checkMemoryNeeds()  // Check decoder needs and supply bytes
        |                 |
        |                 +--> Inner loop for macroop handling:
        |                       |
        |                       +--> processInstructionDecoding()  // Decode and create DynInst
        |                       |
        |                       +--> handleBranchAndNextPC()  // Branch prediction and PC update
        |                       |
        |                       +--> Handle macroop transitions
        |
        +--> Pass stall reasons to decode stage
        |
        +--> Record instruction fetch statistics
        |
        +--> handleInterrupts()  // Handle interrupt processing (FullSystem)
        |
        +--> sendInstructionsToDecode()  // Send instructions to decode with stall reason updates
  |
  +--> updateBranchPredictors()  // Handle branch prediction updates (BTB/FTB/Stream)

checkSignalsAndUpdate()  // For each active thread
  |
  +--> Update per-thread stall statuses
        |
        +--> Process decode block/unblock signals
  |
  +--> Check squash signals from Commit
        |
        +--> Handle branch misprediction squash
        |
        +--> Handle trap squash  
        |
        +--> Handle non-control squash
        |
        +--> Update decoupled branch predictor (BTB/FTB/Stream)
  |
  +--> Process normal commit updates (update branch predictor)
  |
  +--> Check squash signals from Decode
        |
        +--> Handle branch misprediction from decode
        |
        +--> Update decoupled branch predictor
  |
  +--> Check drain stall conditions
  |
  +--> Update fetch status (Blocked -> Running transition)

fetchCacheLine()
  |
  +--> Create memory request(s)
  |
  +--> Send request(s) to I-cache
  |
  +--> Wait for response in recvTimingResp()
        |
        +--> Process received data
        |
        +--> Update fetch buffer
        |
        +--> Update fetch status

lookupAndUpdateNextPC()
  |
  +--> Check if using decoupled frontend
        |
        +--> If DecoupledBPUWithBTB: call decoupledPredict()
        |     |
        |     +--> Get prediction and usedUpFetchTargets status
        |     |
        |     +--> Set instruction loop iteration info
        |
        +--> If non-decoupled: call traditional branchPred->predict()
  |
  +--> Handle non-control instructions (advance PC normally)
  |
  +--> Handle control instructions
        |
        +--> Set prediction target and taken status
        |
        +--> Update branch statistics
        |
        +--> Return prediction result

buildInst()
  |
  +--> Get sequence number from CPU
  |
  +--> Create DynInst with static instruction info
  |
  +--> Set thread-specific information
  |
  +--> For decoupled frontend: set FSQ and FTQ IDs
  |
  +--> Add to CPU instruction list
  |
  +--> Add to fetch queue
  |
  +--> Handle delayed commit flags

// Check if using decoupled frontend
bool isDecoupledFrontend() { return branchPred->isDecoupled(); }

// Different predictor types (目前主要使用BTB)
bool isStreamPred() { return branchPred->isStream(); }
bool isFTBPred() { return branchPred->isFTB(); }
bool isBTBPred() { return branchPred->isBTB(); }  // 主要使用的预测器类型

// Track if FTQ is empty
bool ftqEmpty() { return isDecoupledFrontend() && usedUpFetchTargets; }

class IcachePort : public RequestPort {
    // Handles timing requests to I-cache
    virtual bool recvTimingResp(PacketPtr pkt);

    // Handles retry signals from I-cache
    virtual void recvReqRetry();
};

IcachePort icachePort;

class FetchTranslation : public BaseMMU::Translation {
    // Called when translation completes
    void finish(const Fault &fault, const RequestPtr &req,
                ThreadContext *tc, BaseMMU::Mode mode);
};

// Event to handle delayed translation results
class FinishTranslationEvent : public Event {
    // Process translation result
    void process();
};

FinishTranslationEvent finishTranslationEvent;

// Thread selection policies
ThreadID getFetchingThread();  // Main policy selection function
ThreadID roundRobin();         // Round robin policy
ThreadID iqCount();            // Based on instruction queue count
ThreadID lsqCount();           // Based on load/store queue count
ThreadID branchCount();        // Based on branch count

struct FetchStatGroup : public statistics::Group {
    // Stall statistics
    statistics::Scalar icacheStallCycles;
    statistics::Scalar tlbCycles;
    statistics::Scalar idleCycles;
    statistics::Scalar blockedCycles;

    // Instruction statistics
    statistics::Scalar insts;
    statistics::Scalar branches;
    statistics::Scalar predictedBranches;

    // Performance metrics
    statistics::Formula idleRate;
    statistics::Formula branchRate;
    statistics::Formula rate;

    // Frontend performance metrics
    statistics::Formula frontendBound;
    statistics::Formula frontendLatencyBound;
    statistics::Formula frontendBandwidthBound;
};

void fetch(bool &status_change) {
    ThreadID tid = selectFetchThread();                    // 线程选择
    if (tid == InvalidThreadID) return;

    if (!checkDecoupledFrontend(tid)) return;              // 解耦前端检查

    Addr fetch_addr;
    if (!prepareFetchAddress(tid, status_change, fetch_addr)) return;  // 地址准备

    performInstructionFetch(tid, fetch_addr, status_change);           // 指令获取
}

void performInstructionFetch(ThreadID tid, Addr fetch_addr, bool &status_change) {
    // 主循环: 处理直到fetch宽度或其他限制
    while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize &&
           !predictedBranch && !ftqEmpty() && !waitForVsetvl) {

        // 1. 检查内存需求并供给decoder
        stall = checkMemoryNeeds(tid, this_pc, curMacroop);
        if (stall != StallReason::NoStall) break;

        // 2. 内层循环: 从缓冲的内存中提取尽可能多的指令
        do {
            instruction = processInstructionDecoding(tid, this_pc, next_pc, 
                                                    staticInst, curMacroop, newMacro);
            handleBranchAndNextPC(instruction, this_pc, next_pc, 
                                 predictedBranch, newMacro);
        } while (curMacroop && limitChecks);
    }
}

StallReason checkMemoryNeeds(ThreadID tid, const PCStateBase &this_pc, 
                           StaticInstPtr &curMacroop) {
    // 1. Macroop处理: 如果是macroop，不需要新的内存字节
    if (curMacroop) return StallReason::NoStall;

    // 2. Fetch Buffer检查: 验证buffer有效性和范围
    if (!fetchBufferValid[tid] || PC超出范围) {
        return StallReason::IcacheStall;
    }

    // 3. 字节供给: 为RISC-V提供4字节对齐的数据
    memcpy(decoder->moreBytesPtr(), fetchBuffer + offset, 4);
    decoder->moreBytes(this_pc, fetch_pc);

    return StallReason::NoStall;
}

DynInstPtr processInstructionDecoding(ThreadID tid, PCStateBase &this_pc,
                                     const std::unique_ptr<PCStateBase> &next_pc,
                                     StaticInstPtr &staticInst, 
                                     StaticInstPtr &curMacroop, bool &newMacro) {
    // 1. 指令解码: 普通指令或macroop microops
    if (!curMacroop) {
        staticInst = decoder->decode(this_pc);  // 解码新指令
        if (staticInst->isMacroop()) curMacroop = staticInst;
    } else {
        staticInst = curMacroop->fetchMicroop(this_pc.microPC()); // 获取microop
        newMacro |= staticInst->isLastMicroop();
    }

    // 2. 动态指令创建: 调用buildInst()创建DynInst
    DynInstPtr instruction = buildInst(tid, staticInst, curMacroop, this_pc, *next_pc, true);

    // 3. RISC-V特殊处理: vector配置指令处理
    if (staticInst->isVectorConfig()) {
        waitForVsetvl = decoder->stall();
    }

    return instruction;
}

void handleBranchAndNextPC(DynInstPtr instruction, PCStateBase &this_pc,
                          std::unique_ptr<PCStateBase> &next_pc,
                          bool &predictedBranch, bool &newMacro) {
    // 1. PC状态准备: 保存当前PC到next_pc
    set(next_pc, this_pc);

    // 2. 分支预测: 区分解耦和非解耦前端
    if (!isDecoupledFrontend()) {
        predictedBranch |= this_pc.branching();
    }
    // 对于解耦前端，需要调用lookupAndUpdateNextPC()来更新next_pc，并判断当前pc 是否跳出了当前FTQ，如果跳出了，则需要移动到下一个FTQ
    predictedBranch |= lookupAndUpdateNextPC(instruction, *next_pc);

    // 3. Macroop转换检查: 检查是否移动到新macroop
    newMacro |= this_pc.instAddr() != next_pc->instAddr();

    // 4. PC更新: 设置下一周期的PC
    set(this_pc, *next_pc);
}

enum ThreadStatus {
    Running,           // 真正可以进行instruction fetch，无任何等待
    Idle,             // 线程不活跃，无fetch需求
    Blocked,          // 被下游阻塞，无法继续fetch
    Squashing,        // 正在执行pipeline flush
    TrapPending,      // 等待trap处理（translation fault等）
    WaitingCache,     // 等待任何形式的cache/TLB响应
};

enum CacheRequestStatus {
    CacheIdle,           // 无活跃请求
    TlbWait,            // 等待TLB翻译完成
    CacheWaitResponse,  // 等待cache数据返回
    CacheWaitRetry,     // 等待cache重试机会
    AccessComplete,     // 访问完成，数据可用
    AccessFailed,       // 访问失败（地址无效等）
    Cancelled           // 请求被取消（squash等）
};

// 发起cache请求时
Running → WaitingCache (在fetchCacheLine()中)

// cache完成时  
WaitingCache → Running (在processCacheCompletion()中)

// 异常情况
WaitingCache → TrapPending (翻译失败)
WaitingCache → Squashing (收到squash信号)

bool canFetchInstructions(ThreadID tid) const {
    // 只有真正Running且没有pending cache请求才能fetch
    return fetchStatus[tid] == Running && 
           cacheReq[tid].getOverallStatus() == CacheIdle;
}

bool isWaitingForCache(ThreadID tid) const {
    return fetchStatus[tid] == WaitingCache;
}

bool validateFetchCacheConsistency(ThreadID tid) const {
    auto cacheStatus = cacheReq[tid].getOverallStatus();
    auto threadStatus = fetchStatus[tid];

    // Running状态时，应该没有pending cache请求
    if (threadStatus == Running && 
        (cacheStatus == TlbWait || cacheStatus == CacheWaitResponse || 
         cacheStatus == CacheWaitRetry)) {
        return false;
    }

    // WaitingCache状态时，应该有active cache请求
    if (threadStatus == WaitingCache && cacheStatus == CacheIdle) {
        return false;
    }

    return true;
}